The invention relates to integrated circuits, and more particularly, to an input/output (I/O) signal pad electrostatic discharge (ESD) protection and power supply ESD protection.
Diode and power supply clamps are used as the main workhorse for electrostatic discharge (ESD) protection. However, drastic scaling of technology and decreasing oxide thickness make the known methods insufficient; as it produces a relatively high clamping voltage at the I/O pad.
As electronic components become smaller and smaller along with the internal structures in integrated circuits, it is becoming easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity, even at levels which can neither be seen nor felt. This is typically referred to as ESD, in which the transfer of an electrostatic charge occurs between bodies at different electrostatic potentials (voltages) caused by direct contact or induced by an electrostatic field.
The discharge of static electricity, or ESD, has become a critical problem for the electronics industry. Device failures are not always immediately catastrophic, but often the device is weakened thus less able to withstand normal operating stresses and, hence, may result in a reliability problem. Therefore, various ESD protection circuits must be included in the device to protect the various components, with various considerations necessary for ESD protection circuits.
ESD protection is needed on all pins going to the outside world. While it is a normal strategy to have I/O signal pad ESD protection and power supply ESD protection for digital supplies, because some smaller isolated power supplies may only service small sections of the IC, the overhead of these power supply ESD devices can cause the size of these isolated logic blocks to increase significantly.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.